1. Field of the Invention
The present invention relates to a manufacturing method for an ESD (electrostatic discharge) protection device and, more particularly, to a manufacturing method for a gate-ground MOS transistor used for an ESD protection circuit.
2. Description of the Prior Art
Among current deep sub-micron devices, ggN/PMOS devices have been broadly applied for protecting from ESD. The feature of ggN/PMOS lies in functionality of its parasitic bipolar transistor. When high voltage instantaneously occurs, the parasitic bipolar transistor can be triggered, guiding high current generated by high voltage to the terminal of Vss or Vdd accordingly.
As shown in FIG. 1, by applying the ggN/PMOS circuit structure that functions as an ESD protection device 10 for an integrated circuit (IC), the instantaneous high voltage in the forward direction can activate the parasitic bipolar device of NMOS 12, guiding high current to the Vss terminal. On the other hand, instantaneous high voltage opposite to the forward direction can activate the parasitic bipolar device of PMOS 14, guiding high current to the Vdd terminal. Next, referring to FIG. 2, the principle of the aforementioned structure is that when an ESD phenomenon occurs at the pad of one input terminal, the ggN/PMOS will be triggered and goes into the snapback region. In the snapback region, the ggN/PMOS will clamp on a low-potential voltage that is crossing over the ggN/PMOS and will maintain high current so that the ESD current can be guided out effectively.
Referring to FIG. 3, when the ggNMOS structure used in the processing of non-self-aligned salicide is applied to the ESD protection device, there will be a ballast distance used as a resistance ballast between the drain contact 16 and the polysilicon gate 18, so that when the NPN transistor 20 is triggered, the high current it generates can be discharged in a rather homogeneous manner.
However, in deep sub-micron processing, the self-aligned salicide 22 is applied in the region between the polysilicon gate 18 and the source/drain regions 24 and 16 contained in the ESD structure, as shown in FIG. 4. For this reason, there is hardly any resistance ballast existing between the drain contact 16 and the polysilicon gate 18. Therefore, when electrostatic high voltage is generated, the parasitic NPN (or PNP) transistor in the ESD structure will be triggered correspondingly. Although the current generated by high voltage can be discharged, the collector N of the NPN transistor, which is equivalent to the drain of ggNMOS, has no resistance ballast. In addition to that, the structure of collector N is a shallow junction, which can induce inhomogeneous flow of high current; consequently, partial high current and partial heating phenomenon near the drain can be generated. As a result, the ESD structure can be internally damaged, and the functionality of the ESD protection may fail to perform efficiently.
In view of the aforementioned problem, a manufacturing method for transistor of ESD protection device is provided to solve the drawbacks of the prior arts.